The present application relates generally to semiconductor device manufacturing, and more specifically to approaches for fabricating semiconductor devices using double patterning memorization techniques.
The microelectronics industry continues to strive to incorporate more circuitry having greater complexity onto a single integrated circuit (IC) chip. Achieving this goal generally involves decreasing the size of individual devices within each circuit by decreasing the critical dimension (CD) of device elements together with the pitch or periodicity associated with such elements, i.e., the CD of an element added to the inter-element spacing. Microlithography tooling and attendant processing methods are employed to create the structures used to fabricate devices and, as such, are continually under development to meet industry milestones related to the critical dimension and pitch metrics of each new technology generation.
High numerical aperture (NA) 193 nm optical projection stepper/scanner systems in combination with advanced photoresist processes are capable of defining complex patterns that include isolated and dense resist features having CDs and pitches less than the associated exposure wavelength. However, to meet the requirements of device design rules that continue to challenge the resolution limits of existing processes and tooling, additional more specialized techniques are being developed to further enhance resolution. Such techniques include multi-patterning processes in which device patterns having potentially optically un-resolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each including features with larger CDs and/or a relaxed pitch.
Notwithstanding recent advancements in patterning processing and hardware, it would be advantageous to provide methods for fabricating integrated circuits using multi-patterning processes that provide increased CD uniformity.